We have made significant progress on the development of dense electrophysiological recording platforms exploiting CMOS technology. We have previously demonstrated a 56,000-channel in vitro MEAs for electrical stimulation of neurons. In this project, this MEA has been extended with recording capabilities. This new MEA supports a per-electrode bandwidth of 10 kHz with a sample-rate of 20 kSa/s when recording from the entire chip. The noise efficiency factor (NEF), the established figure of merit for the tradeoff between amplifier (thermal) noise and power, for the amplifier is only 6.8 because of the simplified amplifier design and additional noise introduced with multiplexing in the front end. However, because unused amplifiers can be powered off when not “selected” in a given time interval, tremendous power savings result. With an electrode pitch of 25.4 µm, the amplifier density is better than 1521 amplifiers/mm2. Each effective recording channel has a variable gain up to 80 dB and delivers an input-referred noise of 8V rms over a 100 Hz to 10 kHz bandwidth (and a 22 V rms input-referred noise over a 1 Hz to 400 Hz bandwidth, as suitable for LFP monitoring). Total chip power consumption is 21.8 mW, which amounts to only 0.33 W/channel.
This same dense front-end amplifier design is employed in a 1K-channel prototype uses a standard C4 pitch of 6 mils (152.5 µm). These are designed to be packaged with nanoprobes being developed in Michael Roukes’ group at Caltech. The nanoprobes and the integrated circuit are manufactured separately; allowing us to take advantage (in the prototype) of the unique nanofabrication techniques at Caltech to manufacture the probes, while using IBM’s 65 nm commercial foundry process to design and manufacture the IC itself at low-cost and high yield. The two components are subsequently mated together through C4 flip chip technology.
There are fundamental trade-offs in noise, power consumption, and device area when designing any amplifier for biopotential recordings. Without parsimonious limits on power consumption and device area, it is possible to achieve very low noise, as low as ~2 µV rms for bandwidths up to 20 kHz. However, as power or area, or both, reduces, noise inevitably increases. To provide a solution in which the power does not scale linearly with the number of channels, we have developed a 1024-channel prototype IC that employs the same time-multiplexed front-end approach employed in the active MEA design. Power gating, shutting off amplifiers during the periods of time in which they are not directly in use, allows one to achieve very sublinear power scaling with channel count.
The chip (Figure 4a) contains 1024 sites at the center of the die for connection to the probe array at the 6-mil (150 m) standard C4 pitch. The recording circuit (shown in Fig. 1c) has user-selectable gain up to 60 dB with an input-referred noise of ~8.4 µV RMS from 100 Hz to 10kHz for spike recording, and 17.5 µV RMS over 0.1Hz to 400 Hz for LFP recording (Figure 4c). This is achieved with a thermal-noise-limited input-referred noise of 33.7 nV/Hz1/2 and a noise corner frequency of 7.4 kHz. This flicker noise performance is achieved with nMOS input devices with size of 80 µm2, and providing 34 dB gain in the first stage. A simple quad-transistor front-end amplifier also allows pixel area to be reduced while achieving a noise efficiency (NEF), of only 8.05. The front-end has a programmable high-pass filter with a cut-off that can be as low as 0.1 Hz while requiring a filter capacitance of only 2pF. The IC is able to maintain 10 kHz of bandwidth for each electrode when scanning all 1024 channels. Analog signals are time-multiplexed down to 16 analog output channels. As shown in Figure 4b, part of the input stage of a folded cascade amplifier is duplicated at the pixel level (“first stage front end”), while 64 of these channels are multiplexed to the remainder of the amplifier. This approach means that at most 16 front-end amplifiers are biased at any one time. A second stage of amplification provide an additional programmable gain from 0 dB to 26 dB, giving a maximum overall gain of up to 60 dB through the recording chain. The second amplification stage also provides the capability to drive resistive loads as low as 50 kOhm.
As shown in Figure 5a, this design delivers the lowest power-to-channel ratio and area-to-channel ratio of any designs to date (Figure 5a). More importantly, this 1024-channel prototype consumes less than 12 mW when recording. By comparison, a 32-channel Intan chip uses 15.4 mW. Our 1024-channel prototype also has the lowest-in-class noise given the device area (Figure 5b). The prototype’s noise performance, while not the lowest reported, is more than sufficient for recordings in both the LFP and spike frequency ranges. The relatively large flicker noise corner frequency was tolerated to reduce device area.